Elevate your career with Synopsys as a UVM Verification Engineer, focusing on advanced memory interface IP. Develop robust verification environments and test plans while collaborating with a dynamic team.
As a key player in our IP Group, you will leverage your expertise in SystemVerilog and UVM to enhance verification methodologies. Your responsibilities will include developing detailed test plans, implementing scalable UVM testbenches, and resolving complex debugging challenges. The role demands a strong analytical mindset and excellent communication skills to mentor junior engineers and ensure project alignment across teams.
Key Responsibilities:
• Develop verification test plans for memory interface IP
• Implement UVM testbench infrastructure and robust test cases
• Collaborate with architecture and implementation teams
• Diagnose complex verification challenges using advanced tools
• Research emerging technologies to enhance verification efficiency
Requireme...