Static Timing Analysis Engineer, Full-Chip STA

_corporate_fare_ Google _place_ Mountain View, CA, USA

**Mid**

Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

**Minimum qualifications:**

+ Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
+ 4 years of technical experience in silicon timing closure and chip integration.
+ Experience in one or more static timing tools (e.g., PrimeTime, Tempus).
+ Experience with Static Timing Analysis (STA) signoff constraint authoring for full-chip level, tapeout signoff requirements, checklists, and associated automation.
+ Experience delivering silicon.

**Preferred qualifications:**

+ Master's degree in Electrical Engineering, Computer Science.
+ Experience in extraction of design parameters, QoR metrics, and analyzing data tre...