Overview

Part of the global PCIe/CXL Center of Excellence (CoE) team, developing the latest & state‑of‑the‑art PCIe/CXL solution for next generation FPGA in the latest process technology node.

Responsibilities

Develop logic design, register transfer level (RTL) coding, and simulation for FPGAs to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Participate in the definition of PCIe/CXL architecture and microarchitecture features of the block being designed. Work with IP providers to integrate and validate IPs at the SoC level. Apply various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Review the verification plan and implementation to ensure design features are verified correctly and resolve and implement corrective measures for failing RTL tests to ens...