Overview
RTL-level
digital design and problem solving
Function verification and support
Work closely with backend team on Digital synthesis, place-and-route, Design for Test and Static timing analysis
Lead and guide junior engineers
Digital functional verification and
FPGA verification
Job Requirements
Bachelor/Masters in Electronics/Electrical Engineering with Mixed Signal IC design/verification experience.
At least 7-10 Year(s) of working experience in application/ validation
Fluent in Verilog coding, design, simulation, and verification domains
Definition and implementation of custom digital interfaces (I2C, 3-wire, single_wire etc.)
Definition and implementation of custom finite state machines, register maps, control logic which interface with analog circuits such as drivers and proprietary IPs like OTP or flash memory
RTL design
for synchronous and asynchronous applications, including multiple clock domains
Basic knowledge of Logic s...