Key Responsibilities Key Responsibilities RTL Design and Verification Develop synthesizable RTL in Verilog/SystemVerilog for custom on-chip test, monitoring, and diagnostic IP targeting analog and mixed-signal failure detection. Design and verify digital logic blocks such as test controllers, sequencing logic, sensor/interface control logic, measurement and monitoring logic, data capture and comparison logic, and failure detection and reporting logic. Build clean register and bus-connected interfaces, for example APB, AHB, or AXI-lite based control and status paths, to enable firmware interaction and subsystem integration. Develop testbenches, assertions, checkers, and block or subsystem-level verification environments to validate controller behavior, detection logic, configuration programming, fault response, and status reporting. Plan and execute functional verification for normal, corner, negative, and fault-injection scenarios, with adequate coverage of critical diagnostic behavior...