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Sr. SoC Power Engineer, Annapurna Labs - Cloud Scale Machine Learning
Amazon
๐
Cupertino, United States
Location
Cupertino
Posted
June 20, 2026
Commute
Local Area
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Job Description
Description
Our Machine Learning Acceleration (MLA) team develops the Inferentia and Trainium SoCs that are used to power todayโs AI workloads in datacenters all around the world. As a Sr. SoC Power Engineer, youโll contribute to the project at the ground level by modeling and estimating power at every stage of the design from early RTL to final netlist and by driving ways to reduce power consumption of our machine learning accelerators.
Weโre searching for an experienced SoC Power engineer with a background in Power analysis with a proven track record of handling challenges at scale. In this role, youโll be working directly with architects, designers, verification engineers, software teams, and Physical Design experts - defining best practices to reduce power and model power consumption with high accuracy.
Key job responsibilities
* Responsible for full chip power analysis & modelling at various stages of design (RTL to gate level netlist)
* Develop and main...
Our Machine Learning Acceleration (MLA) team develops the Inferentia and Trainium SoCs that are used to power todayโs AI workloads in datacenters all around the world. As a Sr. SoC Power Engineer, youโll contribute to the project at the ground level by modeling and estimating power at every stage of the design from early RTL to final netlist and by driving ways to reduce power consumption of our machine learning accelerators.
Weโre searching for an experienced SoC Power engineer with a background in Power analysis with a proven track record of handling challenges at scale. In this role, youโll be working directly with architects, designers, verification engineers, software teams, and Physical Design experts - defining best practices to reduce power and model power consumption with high accuracy.
Key job responsibilities
* Responsible for full chip power analysis & modelling at various stages of design (RTL to gate level netlist)
* Develop and main...