Key Responsibilities:

• Responsible for the architecture design, RTL encoding (Verilog/SystemVerilog), and functional verification of digital control logic in 3D-NAND memory;
• Design a state machine (FSM) to manage complex NAND operation processes (such as Program, Read, Erase, Copy-back, Suspend/Resume, etc.);
• Develop a command decoder and address/parameter parsing logic to ensure compliance with JEDEC and internal specifications;
• Implement high-precision timing control logic to accurately generate the internal timing signals required for various operations (such as tR, tPROG, tBERS, etc.);
• Deeply involved in the physical layer and link layer logic implementation of ONFI (Open NAND Flash Interface) or Toggle Mode interface protocols, supporting DDR, NV-DDR, NV-LPDDR, and other modes;
• Collaborate with the analog/mixed-signal team to define array access timing, voltage switching windows, and read/write path control interfa...