Key Responsibilities

• Collaborate with the front-end design team to execute chip floorplanning, clock architecture design, and power planning.

• Lead physical design activities from Netlist to GDSII, including Place & Route (P&R), formal verification, static timing analysis (STA), physical verification, power analysis, design for reliability, and tapeout preparation.

• Research and develop methodologies for advanced process nodes and contribute to the development of automated physical design platforms.

Requirements

• Bachelor’s degree or higher in Electronic Engineering, Microelectronics, Computer Science, or a related discipline.

• Relevant hands‑on experience in backend physical design with proven project involvement; experience in advanced technology node tapeouts is preferred.

• Proficiency in scripting languages such as TCL, Perl, or Python; familiarity with EDA tool...