We are looking for a senior engineer to be part of the mixed-signal design team building next generation NVLINK. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.


We are actively looking for Physical design Engineers with RTL2GDS experience to implement complex high performance and low power SOC’s.


What you'll be doing:
+ Responsible on STA / design constraint for advanced technology nodes.
+ Debugging timing violations and rolling in functional, Timing ECO’s and netlist formal verification.
+ Responsible to Floor Planning and Place and route (P&R) of High-performance chip partitions.
+ Work on power grid planning, Clock tree Synthesis (CTS) and timing closure.
+ Multi mode and multi corner timing closure, RC extraction, Cross talk, IR drop and EM analysis.
+ Physica...