We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deliver high-performance, and power-efficient processors.

Responsibilities

Own and drive physical implementation of CPU blocks from RTL-to-GDSII, focusing on PPA trade-offs. Utilize back-end EDA tool flows, develop/optimize methodologies for synthesis, place-and-route (Pn R), clock tree synthesis (CTS), and timing closure. Work closely with RTL designers to improve timing, area and power efficiency, and evaluate design changes and their impact on PPA. Perform static timing analysis (STA), power analysis, signal integrity checks, and DFT implementation. Optimize floorplanning, clock distribution, power delivery networks, and congestion reduction strategies. Automate design flows and methodologies to improve efficiency and scalability.