20 M gates) with frequencies in excess of 1 GHZ.
- Expertise in block level and full-chip SDC clean up, Synthesis optimization , Low Power checking and logic equivalence checking.
- Familiar with deep sub-micron designs (8nm/5nm) and associated issues (manufacturability, power, signal integrity, scaling).
- Familiar with typical SOC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions.
- Familiar in hierarchical design, top-down design, budgeting, timing and physical convergence.
- Good understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level.
- Should have gone through recent successful SOC tape-outs.
Experience – 5 to 15 Years of experience
Qualifications
- B. Tech/B. E/M. Tech/M. E
Disclaimer
Samsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce an...