Job Description1. Researching and crafting architecture solutions for die-to-die and chip-to-chip communication, optimizing for performance, area, power, security, and resiliency
2. Working with other design teams to define interfaces and flows between D2D blocks and the rest of the chip
3. Architectural modeling, validation, definition and documentation
4. Driving implementation across design, verification, firmware and software teamsRequirement1. Master degree in electrical engineering or computer engineering.
2. 3+ years of experience in Die-to-Die design and architecture.
3. Familiar with RTL design or RTL verification.
4. Experience of SOC architecture design is a plus.