Design and ship high-performance, low-power SRAM and custom-digital sub-systems that sit at the core of our compute-in-memory technology. You will own architecture, circuit implementation, verification, and silicon correlation for advanced nodes, down to sub-5 nm, thereby improving both the efficiency and robustness of our macros. Expect hands‑on work on memory periphery and datapath interfaces, as well as close collaboration with layout, digital, backend, DFT, and test teams.

What you’ll do

• Design and verify embedded SRAM or custom digital blocks, including caches, register files, datapath, and datapath‑adjacent interfaces.
• Optimize for PPA on advanced nodes: variation and stability closure, corners and Monte Carlo, leakage and dynamic power reduction.
• Integrate for product: define clean digital boundaries and timing budgets so blocks drop into a digital‑on‑top flow without surprises.
• Plan and run silicon correlation: bring...