Join Ciena as a Senior ASIC Designer, focusing on high-performance WaveLogic products. Contribute to impactful telecommunications solutions while enjoying a people-first workplace.
In this role, you will utilize your ASIC design expertise to create innovative silicon solutions for critical networks. Collaborate with cross-functional teams to assemble RTL designs and enhance tech libraries. Your efforts will also ensure successful lab validation of ASIC prototypes.
Key Responsibilities:
• Design and integrate ASICS for WaveLogic technologies
• Interpret architecture specifications with engineers and architects
• Develop RTL designs by integrating multiple IP blocks
• Own tool flows for effective ASIC top-level integration
• Validate ASIC prototypes in lab settings
Requirements:
• Bachelor’s degree in Electrical or Computer Engineering
• Minimum 5 years in ASIC design
• Familiarity with Verilog, SystemVerilog, and Python
• Ability to analyze timing and...