Xilinx Asia Pacific Pte. Ltd. is looking for an experienced engineer to design wireline transceiver building blocks, including PLLs and serializers. The ideal candidate should have extensive experience in high speed analog design and leadership skills to present at design reviews globally. A degree in Electronic Engineering (Bachelors, Masters, or PhD) is required. This role is essential for ensuring no bugs in AMD’s SERDES IP final design, focused on cutting-edge process technologies like 7nm or below.
#J-18808-Ljbffr