Job Title: Tech Lead

Location: Redmond, WA

Onsite/ Remote: Onsite

JD:

Design Verification expertise in System Verilog /UVM for Unit/Module level Verification

Strong background in developing UVM Testbenches from scratch

Experience in VIP Integration and Bring up

Porting Existing Verilog/VHDL environment to UVM based Environment

Experience in test planning ,Coverage Coding and Debugging

Deep Knowledge of AMBA Protocol is must

“*** is an Equal Employment Opportunity employer. We promote and support a diverse workforce at all levels of the company. All qualified applicants will receive consideration for employment without regard to race, religion, color, sex, age, national origin, or disability. All applicants will be evaluated solely based on their ability, competence, and performance of the essential functions of their positions with or without reasonable accommodations. Reasonable accommodations also are ava...