Take a leading role as a Principal Engineer in UVM Verification at Synopsys, specializing in advanced memory interface IP. Engage in a dynamic environment dedicated to groundbreaking silicon design solutions.
In this influential position within Synopsys’s IP Group, you will leverage your strong background in SystemVerilog and UVM to develop verification methods. Your responsibilities include creating detailed testplans, working alongside diverse teams, and researching cutting-edge technologies that improve verification processes. You’ll also mentor up-and-coming engineers in your field.
Key Responsibilities:
• Create detailed verification test plans for complex IP models
• Implement scalable UVM testbench architectures
• Collaborate with teams for technical alignment
• Resolve complex verification challenges effectively
• Explore emerging technologies to enhance verification
Requirements:
• Strong proficiency in SystemVerilog and UVM
• Bachelor's degree in...