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Principal Engineer, Design Technology Co-optimization

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Intel
πŸ“ Santa Clara, United States
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Location Santa Clara
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Posted May 30, 2026
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Commute Local Area
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Job Description

**Job Details:**

**Job Description:**

Organization Description

Advanced Design & Foundational IP (ADFIP) is part of Design Technology Platform (DTP) under Foundry Technology Development. ADFIP's core focus is design-technology co-optimization (DTCO), system-design co-optimization (STCO) and foundational IP development to support Intel technology development, internal client/server/NEX products and external tie0/tie1 customers. The organization develops logic libraries, memories, high-speed I/Os, analog and mixed signal IPs, RF/mmWave circuits and 3D IC, and conducts comprehensive Si validation on process and package development test vehicles and FIP characterization vehicles. Advanced power, performance and area (PPA) analysis is conducted across domains to guide silicon and packaging technology definition to maximize technology PPA entitlement and minimize process risks and cost.

Job Role & Responsibility Description
As a logic library vertical l...

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πŸ“ Location Details

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City
Santa Clara
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Country
United States
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Commute
Local Area

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