PLL Architect and Design Engineer

Responsibilities

• Address challenges in advanced node technologies, such as self‑heating, electromigration, voltage‑controlled oscillator (VCO) linearization and device‑level noise optimization.
• Architect, design and simulate analog/mixed‑signal PLL building blocks (VCOs, charge pumps, dividers, PFDs, loop filters) at transistor level using tools such as Cadence Virtuoso and Spectre.
• Be responsible for PLL bring‑up in the lab and conduct performance characterization using state‑of‑the‑art lab equipment.
• Conduct comprehensive system‑level simulations and validation for PLL integration into advanced transceiver technologies.
• Supervise and verify layouts produced by layout engineers to ensure floorplanning, matching, and parasitic minimization using advanced node technologies.
• Understand trade‑offs between different PLL topologies (integer‑N, fractional‑N, all‑digital/ADPLL) ...