Job Summary

• Apply comprehensive expertise in RTL to GDSII design flow and lead the full physical design process for SoC projects.
• Collaborate with cross-functional teams to ensure design sign-off through verification and timing closure.
• Drive quality and efficiency in chip development.

Responsibilities

• Execute the full physical design flow for SoC top-level projects, ensuring timely and accurate delivery of design milestones.
• Apply deep knowledge of Place and Route (PnR) flow to optimize chip layout and performance.
• Perform sign-off activities including Design Rule Check (DRC), Layout Versus Schematic (LVS), and Static Timing Analysis (STA) to verify design integrity and timing closure.
• Utilize EDA tools such as Genus, Innovus, Quantus, and Redhawk proficiently to support design implementation and verification.
• Develop and maintain TCL and Perl scripts to automate design ta...