Main Job Tasks and Responsibilities

• Participating in or leading next-generation physical design, methodology, and flow development in advanced technology nodes.
• Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.

Position Requirements

• Bachelor or above degree in majors of EE/CS/IT, with 5+ years work experience
• Extensive knowledge of design rule for the process of N7/N5 and below
• Knowledge of scripting languages and use in methodology
• Ability to fix physical design violations, including: DRC, DFM, LVS, ANT, ERC etc.
• Deep experience of static timing analysis
• Ability to learn quickly
• High level of communication and teamwork
• Carefulness, responsibility, and persistence