Should be able to handle Full chip hashtag
Added advantage for #Innovus with Minimum 4 years
#Pn R (timing/congestion/CTS issues), understanding of hashtag
#IO ring,
#package support, multi hashtag
#voltage design.
Deep understanding of the concepts related to hashtag
#synthesis , place & route, hashtag
#CTS , timing convergence, IR/EM checks and signoff DRC/LVS closure.
Responsible for independent planning and execution of all aspects of physical design including
#floor_planning ,
#place_and_route ,
#Clock_Tree_Synthesis , Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, hashtag
#Physical_Verification ,
#DFM.
Must have participated in all stages of the design (floor planning, placement, CTS, routing, physical verification,
#IREM ).
Well versed with the timing closure ( #STA ), timing closure methodologies
Good Understanding of DRC, LVS,
#ERC and PERC rule files for lower tech node layout veri...