Job Title: Backend So C Lead
Experience- 12+ years
Location: Bangalore
Key Responsibilities-
End-to-end Pn R — floorplan to GDS handoff — on advanced Fin FET nodes.
Timing closure with AOCV / POCV across PVT corners; late-stage ECO management.
Physical sign-off: DRC, LVS, ERC, power integrity (IR drop / EM).
Low-power implementation: multi-voltage, power gating, retention, DVFS.
Lead & mentor 5–15 backend engineers through tape-out milestones.
Primary technical interface with client program teams.
Must have-
12+ years backend physical design; tapeout ownership at 16 nm or below.
Innovus or ICC2 for Pn R; Prime Time or Tempus for STA Calibre DRC / LVS sign-off and foundry rule resolution Tcl scripting for flow automation; Python a strong plus
Process nodes: TSMC 5 nm TSMC 7 nm TSMC 12 nm TSMC 16 nm Samsung 4 nm GF 12 nm GF 22 FDXTSMC 22 nm.
Tools : P&R Cadence Innovus, Synopsys ICC2 STA Prime Time, Tempus Phys Ver Mentor Calibre DRC / LVS / ERC ...