Job Description1. Serdes/High speed interface related PHYD IP architecture planning
2. Serdes/High speed interface related PHYD IP RTL coding
3. Serdes/High speed interface related PHYD IP front-end and back-end integration
4. Co-work with MAC design team and DV team for IP verification
5. Co-work with Analog design team for PHY co-simulation

#LI-DC3Requirement1. Good at RTL and digital circuit design
2. Familiar with front-end or back-end integration flow and related EDA tools
3. Knowledge of high speed interface standards such as Ethernet Serdes, PCIe, USB, HDMI, DP, MPHY, CPHY etc.
4. Experience in high speed Interface PHYD IP development
5. Experience in DSP based IP design, such as CDR, CTLE, FEC, FFE, FIR, IIR etc.