## Mixed Signal Design Verification EngineerApplylocations: Malaysia, Penangtime type: Full timeposted on: Posted Todayjob requisition id: JR # **Job Details:**## Job Description:CEG HIPD MYS is seeking mixed-signal design engineer to join our talented and vibrant team. You will be directly involved in delivering next-generation DDR PHY designs for SOC application on Intel leading process node.Key Responsibilities include but not limited to• Develop a Mixed-Signal Validation (MSV) testbench in accordance with the specified requirements.• Own MSV for Custom Building Blocks (CBB) which covering open loop functional checks, closed-loop functional checks with RTL blocks, PHY level features, high volume manufacturing (HVM) features, closed-loop with Memory Reference Code(MRC) checks.• Independently analyze the result based on specification documents and debug the root cause of the failures.• Participate in MSV result review and collaborate with designers.## **Qualifications:**Prefer...