Experience: 4- 8 years
Location - Bangalore/Pune
Responsibilities:
· Complete DFT ownership of projects including:
Identifying and implementing RTL changes for DFT.
Performing scan insertion, LEC checks, low power CLP checks.
Developing timing constraints for test mode timing closure.
Scan and ATPG for different fault models.
Boundary scan, ACJTAG, IEEE 1500 implementation and verification.
IEEE1687 (i JTAG) compliant ICL/PDL for functional manufacturing tests.
Running zero delay and timing simulations and debugging on all the above aspects.
Supporting post silicon bring up.
Experience working on very high speed and low power designs.