Description: JOB DUTIES: This position will be responsible for leading the development and execution of electrical validation test plans for a new high speed memory interface for high performance CPUs. Duties will include but not be limited to: Organizing and running regular engineering meetings. Ability to perform debug of failing test plans and /or CPU interfaces. Delivering regular status updates via PowerPoint or similar. Analysis of test results and determining next steps for validation / experimentation. Operate high speed oscilloscopes and related equipment to measure and test high speed ASIC I/O. Develop and analyze I/O characterization test plans for upcoming ASIC products. Execute and or supervise the execution of I/O characterization test plans. Developing and debugging automation for benchtop test flows. Develop and analyze scripts in PERL or similar language to facilitate and automate test sequences.



EXPERIENCE AND EDUCATION: