Hi All, I have an urgent Opening for STA & Synthesis - Bangalore location. Exp -5 to 8 yrs Notice Period - Immediate to 15 days. Location - Bangalore JD: Working knowledge of Synthesis, LEC and STA and concepts behind it. Block level synthesis & sub-top/top level timing signoff, generating timing ECOs with hierarchical scope. Feedback to RTL design on lint and timing issues from block & sub-top-level STA. Experience with Genus, Conformal and Tempus tool is must. Proficient in TCL, Python etc. Good understanding of multiple clock domain timing analysis, OCV/AOCV/SOCV and clock tree concepts Good written and verbal communication skills and aptitude. Interested candidates, kindly share with me your updated profile to.