Hi All,

I have an immediate requirements for Analog layout - Hyd location

Exp - 4 to 7 yrs
NP - Immediate
Mode of interview - F2F only in Hyd

JD:

Key Responsibilities:
End-to-end design and development of critical

analog, mixed-signal, and custom digital blocks , along with

full-chip integration support .
Responsible for

timely delivery

of high‑quality block-level layouts.
Perform

verification flows

including LVS, DRC, DFM, Antenna checks, and EMIR.
Work independently with cross-functional teams.

Mandatory Skills & Tools:
Strong hands-on experience in

TSMC lower nodes (3nm / 5nm / 7nm / 12/16nm) .
Experience with Intel, Samsung, or GF nodes is acceptable, but

TSMC is mandatory .
Expertise in

Cadence VLE/VXL

and

Mentor Graphics Calibre (DRC/LVS) .
Good experience with

analog block layouts

such as R...