Responsibilities

• Synthesize Verilog RTL and create models; compile them to emulators like Veloce, Palladium, Zebu, or FPGA platforms.
• Develop all aspects of hardware emulator implementation, focusing on design partitioning, synthesis, place and route, timing analysis, and runtime performance.
• Drive debug of failure on emulator using latest technologies; collaborate with designers and software driver team for test planning and debugging.
• Work with tool vendors and improve methodology to increase area/performance of the synthesized FPGA RTL.
• Integrate third‑party IP and perform system‑level debugging.
• Conduct system level RTL simulation and design verification.
• Support chip bring‑up and post‑silicon debug.
• Debug functional and timing models.

Preferred Qualifications

• Bachelor's degree in Science, Engineering, or closely related field.
• 3+ years of hands‑on experience in e...