Ciena is hiring a Frontend ASIC Synthesis Engineer to drive innovations in high-speed optical networking. Leverage your expertise in static timing analysis and synthesis for impactful project contributions.
This role at Ciena offers the chance to work on groundbreaking DSP programs, requiring a strong foundation in ASIC verification techniques. As a key player, you will execute frontend design tasks and collaborate across teams to enhance product performance. Your work will make a significant impact on project outcomes while ensuring high standards of quality.
Key Responsibilities:
• Lead frontend synthesis for assigned ASIC subsystems
• Develop integration timing constraints
• Validate RTL against gate-level netlists
• Ensure clock domain crossing integrity for top-level designs
• Optimize workflows using scripts and tools
Requirements:
• B.Sc. in Electrical or Computer Engineering
• Proficient in synthesis and timing analysis tools
• Solid understandi...