Front End ASIC RTL/Logic Verification Engineer
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Job Description
Job Overview
Develops the verification plan to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
Supports SoC customers to ensure high-quality integration and verification of the IP block.
Drives quality assurance compliance for smooth IPβSoC handoff.
Qualifications
- BS/MS or PhD in Electronics Engineering
- Strong in communication, leadership, investigation, problem solving & analytical skill
- Proficiency with RTL coding using HDL language(s). Familiarity with logic simulation and debug environments
- Knowledge of scripting is an advantage
Job Details
Job Type: Regular
Shift: Shift 1 (Malaysia)
Primary Location: Penang, 15, Penang, Malaysia
Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, co...