Summary

Entry-level role focused on developing, executing, and automating device modeling tests within Altera Quartus Prime flows. You will validate FPGA device models, timing models, and related collateral used by synthesis, place‑and‑route, and timing analysis. The role blends FPGA design fundamentals, EDA flow execution, software development, and test automation to ensure model quality, correctness, and regression stability across device families.

Test Planning and Execution

• Develop test plans for device and timing model validation across Quartus Prime components (Compilation, Fitter, TimeQuest, Assembler).
• Execute targeted and regression tests for multiple FPGA device families, configurations, and corner conditions.
• Validate constraints (SDC) interpretation, timing arcs, and model parameterization consistency.

Flow and Infrastructure

• Build and run end‑to‑end Quartus projects to exercise synt...