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Engineer ( Yield Enhancement )
Vanguard International Semiconductor Corporation (VIS)
📍
singapore, Singapore
Location
singapore
Posted
June 25, 2026
Commute
Local Area
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Job Description
- To liaise with module engineers on defect excursion control
- To drive for defect reduction and yield improvement activities
- Supervise YE Associate Engineers and wafer tech operators to ensure smooth 24/7 inline shift operation
- Train and certify YE Associate Engineers on recipe creation and defect source knowledge
- Maintain and enhance internal SOP/OCAP and involve in internal;/external audit
- Operate FIB/SEM/EDX/OM for inline failure analysis
- Operate and create recipes in Brightfield, Darkfield and other defect inspection tool
- Perform partition analysis on defect source and detailed reports on issues
- Build and develop defect source library.
- Track inline defect performance by layer/process tool/chamber on weekly basis
- Perform defect characterization by process tools
- Continuous improvement activities on defect reductions with Modules / vendor...