About the Role

This role sits at the intersection of the AiWACS radar signal processor and the PAiREGRINE onboard compute stack. You will develop the FPGA-based low-latency preprocessing pipeline that fuses radar, EO/IR, thermal, and RF data for real-time edge inference on the drone.

Key Responsibilities

• Develop FPGA firmware (VHDL/Verilog) for real-time radar signal processing (pulse compression, beamforming, CFAR detection)
• Build low-latency data pipelines from sensor inputs (ADC, camera, RF receiver) through FPGA to ARM/Jetson compute modules
• Implement real-time AES-256 encrypted datalink telemetry (FHSS, MANET/MIMO radio integration)
• Develop and optimise embedded C/C++ firmware for flight computer and mission processor
• Integrate with ROS-based autonomy stack for UAV sensor fusion and mission execution
• Support hardware-in-the-loop (HIL) testing and radar receiver characterisatio...