Job Description1. SoC chip integration from RTL to gate level including timing closure and testability
2. Whole chip DFT structure planning and design
3. Whole chip timing review and closure sign-off
4. Design methodology and integration flow improvement
5. Chip TOP IO and floorplan planning and TOP glue circuit design
6. Work location: Hsinchu/Taipei

#LI-LL1Requirement1. Chip level integration experience
2. Familiar with frontend or backend implementaion flow and related EDA tools
including: DFT/BSD/TestKompress, Tempus/PrimeTime/PrimeClosure
3. Experience about DFT Integraiton or STA timing sign-off
4. Solid knowledge of clock, timing constrain, CTS and physical implementation