As a member of our Mixed-Signal high-speed I/O SerDes group, you'll be working on NVDIA's latest ground breaking technology that enables and accelerates gaming, artificial intelligence, deep learning, and autonomous driving. Your design will be consumed by standard as well as industry-leading proprietary high-speed protocols, and will serve as one of the key IPs in many complex SoC. You'll work closely with analog designers and system architects to independently come up with micro-architecture specification and refine adaptation algorithms. You'll then implement the RTL in SystemVerilog, define test cases that will deeply verify the design and carry out test creations. Next is to define and build constraints for synthesis and drive for timing closure. In addition to RTL design, you'll need to understand the analog schematics and write SystemVerilog models that collects the functionality of those circuits in the most precise way.


What you'll be doing:
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