Join as a Digital ASIC Verification Engineer and take the lead in developing and verifying innovative ASIC designs in a geographically diverse team.

You'll play a crucial role in creating verification infrastructure and executing thorough test plans that adhere to stringent functional and standards requirements. Your expertise with System Verilog and your understanding of UVM will empower you to run effective self-checking tests on complex digital ASICs.

Key Responsibilities: • Lead verification infrastructure development for ASICs • Create protocol and traffic generators using System Verilog • Develop comprehensive test plans for verification • Define and execute self-checking tests for designs

Requirements: • Bachelor’s in Computer Science or Electrical Engineering • Over 8 years of ASIC verification experience • Proficient in System Verilog and Python • Deep knowledge of UVM methodology • Strong communication abilities in a distributed environment