The DFT architect / lead engineer serves as a technical authority and strategic lead in designing and deploying industry-leading Design-for-Test (DFT) architectures. This role is responsible for the end-to-end DFT strategy for complex, high-performance SoCs—spanning architectural definition, advanced ATPG/MBIST/LBIST strategies, and silicon lifecycle management. You will drive innovation in test methodology to achieve world-class quality, minimize test cost, and ensure seamless transition from pre-silicon RTL to high-volume manufacturing (HVM).
Your Job

+ Architectural Leadership: Define and own the global DFT architecture, including Hierarchical Scan, Compressed ATPG, Memory BIST/Repair (BISR), Logic BIST, and IEEE 1687 (IJTAG) networks for multi-die or chiplet-based designs.

+ Test Strategy Optimization: Develop advanced strategies for defect-oriented testing and optimize pattern volumes to balance aggressive coverage targets with tester memory constraints and ...