Commitment Period: Jan 2026 onwards (Full-time Internship, min. 6 months)

Job Description

As design verification engineer, you would be part of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation and formal verification. The goal is simple – to achieve zero-defect with the best and smartest approach to the large verification space.

Requirements:

1. Disciplined, quality-minded, and highly driven for excellence
2. Excellent team player and good communication skills
3. MSEE/BSEE in Electrical Engineering or Computer Engineering
4. Experience in UVM verification methodology is a plus
5. Knowledge in deep learning algorithms such as CNN / Transformeris a plus
6. Experience in NPU / GPU / DSP v...