Hiring Alert | Senior Analog Layout Design Engineers / Leads Greetings from Eximietas Design! We are actively hiring Senior Analog Layout Design Engineers / Leads with 8–12 years of experience to join our growing VLSI team. Location: Bengaluru Notice Period: Immediate joiners preferred Preferred Hands On: TSMC 3nm & SERDES Key Skills & Requirements: Strong expertise in lower FINFET technology nodes ( TSMC 3nm & SERDES preferred) Experience in IR drop, Electromigration (EM), self-heating, RC delay, and parasitic capacitance optimization Good understanding of layout impact on circuit performance (speed, area, power, etc.) Ability to deliver high-quality layouts under tight design constraints Hands-on experience with CADENCE / SYNOPSYS layout tools and flows Scripting knowledge (PERL / SKILL) is an added advantage Strong communication skills and experience working with cross-functional teams If you're interested or know someone suitable, please share your updated resume at: Referrals are ...