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Cellular SoC Static Timing Analysis Engineer
Apple
๐
Sunnyvale, United States
Location
Sunnyvale
Posted
June 03, 2026
Commute
Local Area
Local Opportunity Near You!
This job is in your area. Enjoy a short commute and work close to home.
Job Description
**Role Number:** 200628423-3956
**Summary**
Do you have a passion for invention and self-challenge? Do you thrive on pushing the limits of whatโs considered feasible. As part of a world class modem team, you'll be at the heart of chip design! Apple recently announced first in-house 5G modem platforms, the C1 and C1X, developed to deliver industry-leading connectivity performance, improved energy efficiency, and seamless integration with Appleโs custom silicon. Youโll ensure Apple products and services can seamlessly handle the tasks that make them beloved by millions. Join us, and youโll help us innovate new cellular technologies that continually outperform the previous iterations! Do you want to have an impact on every single Apple product?
As an ASIC STA engineer, you will be responsible for all aspects of timing including, working with designers for timing constraints generation, helping construct/modify flows, timing analysis and timing closure.
**Descripti...
**Summary**
Do you have a passion for invention and self-challenge? Do you thrive on pushing the limits of whatโs considered feasible. As part of a world class modem team, you'll be at the heart of chip design! Apple recently announced first in-house 5G modem platforms, the C1 and C1X, developed to deliver industry-leading connectivity performance, improved energy efficiency, and seamless integration with Appleโs custom silicon. Youโll ensure Apple products and services can seamlessly handle the tasks that make them beloved by millions. Join us, and youโll help us innovate new cellular technologies that continually outperform the previous iterations! Do you want to have an impact on every single Apple product?
As an ASIC STA engineer, you will be responsible for all aspects of timing including, working with designers for timing constraints generation, helping construct/modify flows, timing analysis and timing closure.
**Descripti...