At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
We are seeking a ATE Test Engineering Architect to lead development and deployment of production test solutions for our large complex SoCs deployed in our Emulation Products. This role owns ATE test strategy and execution from first silicon bring‑up through qualification and high‑volume manufacturing, working closely with design, DFT, and global manufacturing partners.


This is a hands‑on technical leadership role for engineers passionate about silicon quality, yield, and scalable test solutions.


Job Responsibilities:

+ Lead ATE test development for wafer sort (CP) and final test (FT)

+ Drive first‑silicon bring‑up, debug, and characterization

+ Define test coverage, binning, guard‑banding, and production release criteria

+ Analyze yield and failure data; drive test‑related yield and quality impro...