Hiring – ASIC RTL Design Engineer (5+ Years Experience)

We are actively looking for experienced ASIC RTL Design Engineers to join our team.

Experience: 5+ Years

Location: Bangalore / Hyderabad

Required Skills:

• Strong experience in ASIC RTL Design using Verilog/System Verilog
• Solid understanding of SoC Microarchitecture and RTL implementation
• Hands-on experience with high-speed interface protocols such as MIPI and LPDDR
• Experience in SoC integration, RTL development, synthesis, lint, CDC, and timing analysis
• Good understanding of ASIC design flow and methodology
• Strong debugging, problem-solving, and communication skills

Preferred:

• Experience ...