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ASIC Layout Engineer - Analog, High speed IP - 8 to 11 years - Bangalore
Cisco
📍
Bangalore, India
Location
Bangalore
Posted
June 08, 2026
Commute
Local Area
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Job Description
**What You'll Do**
We are looking for a talented and motivated **Layout Lead** to join Cisco’s Client Optics Group (COG) Engineering Team. In this role, you will support the physical implementation of high-performance analog and mixed-signal circuits for next-generation 100G, 200G, and 400G per lambda optical interconnect solutions.
You will contribute to all phases of physical design—from concept through tapeout—primarily for block-level layouts while assisting with top-level integration. Working closely with circuit designers, packaging engineers, process teams, and product engineers, you will help develop robust, manufacturable layouts that meet performance, reliability, area, and schedule goals.
**Specific responsibilities include:**
+ Support layout development and physical implementation of analog, mixed-signal circuits, high-speed interfaces (including SerDes and PAM4), and supporting digital blocks
+ Participate in block-level floorplann...
We are looking for a talented and motivated **Layout Lead** to join Cisco’s Client Optics Group (COG) Engineering Team. In this role, you will support the physical implementation of high-performance analog and mixed-signal circuits for next-generation 100G, 200G, and 400G per lambda optical interconnect solutions.
You will contribute to all phases of physical design—from concept through tapeout—primarily for block-level layouts while assisting with top-level integration. Working closely with circuit designers, packaging engineers, process teams, and product engineers, you will help develop robust, manufacturable layouts that meet performance, reliability, area, and schedule goals.
**Specific responsibilities include:**
+ Support layout development and physical implementation of analog, mixed-signal circuits, high-speed interfaces (including SerDes and PAM4), and supporting digital blocks
+ Participate in block-level floorplann...