**Meet the Team**

Define, design and verify ASIC and ASIC subsystems to be deployed in a range of Cisco platforms. Contribute to a multi-disciplined engineering team to meet the power, performance, and area goals for products. Design, document, and develop ASIC subsystems for release in high volume and quality. Help define the process, methods, and tools for design and implementation of complex developments.

**Your Impact:**

Collaborate with Front-end and Back-end teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure. As part of this team, you will contribute to develop next generation networking chips.

You need to possess a deep understanding of timing constraints, including clock groups, exceptions, and clock exclusivity. Proficient in industry standard SDC/DTA tools and scripting for automation. Excel at identifying and resolving timing issues across all design levels.