NVIDIA Clocks and Resets group is looking for a top ASIC engineer with extensive experience in high-speed logic design and gate-level design implementation and optimization! The complexity of clocking structure has grown significantly over years with increased focus on performance and power. Modern clocking designs need to balance high frequency clocks with power optimizations, DFT, crosstalk, routing and other physical implementation and timing closure constraints. We need a dedicated and motivated engineer to work on next generation Clocking implementation for Tegra SOCs.

What you'll be doing:

• Micro-architect and Design new clocks modules and topologies in order to support all IPs constituting the SOC.

• Understand and evaluate the trade-offs across DFX, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL.

• Collaborate with multiple other SOC fun...