Responsibilities
Responsibilities
· Define and evaluate architectural features for next-generation AI inference chips.
· Analyze Transformer and LLM workloads to identify performance, power, area, memory, and latency bottlenecks.
· Explore AI accelerator architectures and microarchitectures, including compute arrays, memory hierarchy, NoC, DMA, scheduling, and dataflow.
· Work on hardware-software co-design for LLM inference, including operator mapping, tiling, memory planning, and compiler-guided optimization.
· Collaborate with algorithm, compiler, RTL, verification, and software teams to deliver implementable architecture solutions.
· Propose novel architecture ideas and contribute to patents and technical documentation.
Qualifications
· Bachelor’s degree or above in Computer Engineering, Computer Science, Electrical Engineering, or related fields.
· Strong knowledge of computer architecture, AI accelerators, memory hierarchy, interconnect, and performa...